Electronics and Communication Engineering

• • ASIC Implementation of 8 BIT RISC Processor-
    This project presents a 8-bit RISC processor design and ASIC implementation using Verilog Hardware Description Language (HDL). The processor is designed using Harvard architecture, having separate instruction and data memory. Its most important feature is that its instruction set is very simple, contains only 29 instructions, and another important feature is pipelining, used for improving performance
  • ASIC Implementation of 32-bit RISC V –
    As IC chip design involves complex computations and intense usage of resources, by using an HDL we can save resources and time by implementing it using the software approach.The objective of the project is to design and implement a 32-bit RISCV Processor using Verilog (Hardware Description Language). The implementation strategies have been followed the RISC architecture. The processor has 32-bit arithmetic and logical instruction set which has been designed and simulated.
  • Design and Implementation of 16-Bit MIPS Processor-
    MIPS 16 enables embedded system designers to reduce costs by decreasing the size of memory required to run their application by up to 40 percent compared to traditional 32-bit software implementations.In addition to providing advanced code density, MIPS 16 also achieves a high level of power efficiency, and performance equivalent to that of 32-bit only implementations. MIPS 16 also improves instruction cache hit rate. It is supported by hardware and software development tools from MIPS and other providers.
  • ASIC Implementation of Scalable Encryption Algorithm for Miniaturized Gadgets-
    SEA is a scalable encryption algorithm widely utilized miniaturized devices and it is predominantly designed for its enactment in processors with a limited instruction set and throughput requirement. The work reported the ASIC implementation of SEA using Cadence EDA tool. The power consumption and delay was found to be 78.11 µW, 690 pS .
  • Design and Implementation of Double Precision Floating-Point Unit Architecture-
    The main Aim of the Project is to Design and implementation of floating point architecture. Floating point numbers are the quantities that cannot be represented by integers, either because they contain fractional values or because they lie outside the range re presentable within the system’s bit width. Multiplication of two floating point numbers is very important for processors. Architecture for a fast floating point multiplier yielding with the single precision IEEE 754-2008 standard has been used in this project. 
  • Design of Compressors for Fault Tolerant Application-
    Approximate multipliers are widely being advocated for energy-efficient computing in applications that exhibit an inherent tolerance to inaccuracy. Approximate circuits have been considered as a potential alternative for error-tolerant applications to trade off some accuracy for gains in other circuit-based metrics, such as power, area and delay.
    In this work approximate arithmetic circuits such as adders and Multipliers are designed.
    Bitwise pixel addition and subtraction of two gray scale images of the same size is performed by using approximate adder circuit and compared with the images obtained by exact addition and subtraction method.
  • Brain Computer Interface-
    A mind PC interface (BCI), once in a while called a direct brain interface or a cerebrum machine interface, is an immediate correspondence pathway between a human or creature mind and an outer gadget. In one-manner BCIs, PCs either acknowledge orders from the mind or convey messages to it (for instance, to reestablish vision) yet not both. Two-way BCIs would permit cerebrums and outside gadgets to trade data in the two headings however presently can’t seem to be effectively embedded in creatures or people.
  • ASIC Implementation of Halftone Pixel Image Conversion-
    Halftone is the reprographic technique that simulates continuous-tone imagery through the use of dots, varying either in size or in spacing, thus generating a gradient-like effect. “Halftone” can also be used to refer specifically to the image that is produced by this process

Events

• Organized a One days WORKSHOP on INTERNET OF THINGS from 28^th September 2018, held at Centurion University of Technology & Management (CUTMAP) Viziangaram.
• Organized a Three days WORKSHOP on Applied electromagnetic Antennas EMI/EMCfrom 29^th MAY -31^st 2019, held at Centurion University of Technology & Management (CUTMAP) Viziangaram.